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figure 1. typical application C not a simpli?ed circuit (a) and output characteristic tolerance envelopes (b). table 1. notes: 1 . typical output power for designs in an enclosed adapter measured at 50 c ambient. 2 . uses higher re?ected voltage transformer designs for increased power capability C see key application considerations section. 3 . for lead-free package options, see part ordering information. february 2005 lnk501 linkswitch ? family energy ef?cient, cv/cc switcher for very low cost chargers and adapters pi-2776-022603 wide range hv dc input dc output (v o ) (a) (b) for circuit shown above with optional secondary feedback** *estimated tolerance achievable in high volume production including transformer and other component tolerances. **see optional secondary feedback section. linkswitch v o i o 10% 20%* v o i o 5% 20%* d s c output power table 1 product 3 230 vac 15% 85-265 vac no-load input power lnk501p or g 4 w 3 w <300 mw 5.5 w 3.5 w <500 mw 2 product highlights cost effective linear/rcc replacement ? lowest cost and component count, constant voltage, constant current (cv/cc) solution ? extremely simple circuit con?guration ? up to 75% lighter power supply reduces shipping cost ? primary based cv/cc solution eliminates 10 to 20 secondary components for low system cost ? combined primary clamp, feedback, ic supply, and loop compensation functions C minimizes external components ? fully integrated auto-restart for short circuit and open loop fault protection C saves external component costs ? 42 khz operation simpli?es emi ?lter design ? 3 w output with ee13 core for low cost and small size much higher performance over linear/rcc ? universal input range allows worldwide operation ? up to 70% reduction in power dissipation C reduces enclosure size signi?cantly ? cv/cc output characteristic without secondary feedback ? system level thermal and current limit protection ? meets all single point failure requirements with only one additional clamp capacitor ? controlled current in cc region provides inherent soft-start ? optional opto feedback improves output voltage accuracy ecosmart ? C extremely energy ef?cient ? consumes <300 mw at 265 vac input with no load ? meets california energy commission (cec), energy star, and eu requirements ? no current sense resistors C maximizes ef?ciency applications ? linear transformer replacement in all 3 w applications ? chargers for cell phones, cordless phones, pdas, digital cameras, mp3/portable audio devices, shavers, etc. ? home appliances, white goods and consumer electronics ? constant output current led lighting applications ? tv standby and other auxiliary supplies description linkswitch is speci?cally designed to replace all linear transformer/rcc chargers and adapters in the 3 w universal range at equal or lower system cost with much higher performance and energy ef?ciency. linkswitch introduces a revolutionary topology for the design of low power switching power supplies that rivals the simplicity and low cost of linear adapters, and enables a much smaller, lighter, and attractive package when compared with the traditional brick. with ef?ciency of up to 75% at 3 w output and < 300 mw no-load consumption, a linkswitch solution can save the end user enough energy over a linear design to completely pay for the power supply cost in less than one year. linkswitch integrates a 700 v power mosfet, pwm control, high voltage start-up, current limit, and thermal shutdown circuitry, onto a monolithic ic.
2 i 2/05 lnk501 pin functional description drain (d) pin: power mosfet drain connection. provides internal operating current for start-up. internal current limit sense point for drain current. control (c) pin: error ampli?er and feedback current input pin for duty cycle and current limit control. internal shunt regulator connection to provide internal bias current during normal operation. it is also used as the connection point for the supply bypass and auto-restart/compensation capacitor. source (s) pin: output mosfet source connection for high voltage power return. primary side control circuit common and reference point. figure 3. pin con?guration. pi-2711-073107 s d s s s c 5 7 8 s 4 2 3 1 p package (dip-8b) g package (smd-8b) lnk501 figure 2. block diagram. pi-2777-032503 shutdown/ auto-restart pw m comparator clock saw oscillator internal supply 5. 6 v 4. 7 v source s r q d max - + control - + 5.6 v i fb z c v c + - edge 0 1 hystereti c thermal shutdown leading edge blanking current limi t adjust low frequency operation shunt regulator/ error amplifier + - drai n i dcs current limi t comparator r e 8
3 i 2/05 lnk501 linkswitch functional description the duty cycle, current limit and operating frequency relationships with control pin current are shown in figure 4. figure 5 shows a typical power supply outline schematic which is used below to describe the linkswitch operation. power up during power up, as v in is ?rst applied (figure 5), the control pin capacitor c1 is charged through a switched high voltage current source connected internally between the drain and control pins (see figure 2). when the control pin voltage reaches approximately 5.6 v relative to the source pin, the high voltage current source is turned off, the internal control circuitry is activated and the high voltage internal mosfet starts to switch. at this point, the charge stored on c1 is used to supply the internal consumption of the chip. constant current (cc) operation as the output voltage, and therefore the re?ected voltage across the primary transformer winding ramp up, the feedback control current i c increases. as shown in figure 4, the internal current limit increases with i c and reaches i lim when i c is equal to i dct . the internal current limit vs. i c characteristic is designed to provide an approximately constant power supply output current as the power supply output voltage rises. constant voltage (cv) operation when i c exceeds i dcs , typically 2 ma (figure 4), the maximum duty cycle is reduced. at a value of i c that depends on power supply input voltage, the duty cycle control limits linkswitch peak current below the internal current limit value. at this point the power supply transitions from cc to cv operation. with minimum input voltage in a typical universal input design, this transition occurs at approximately 30% duty cycle. resistor r1 (figure 5) is therefore initially selected to conduct a value of i c approximately equal to i dct when v out is at the desired value at the minimum power supply input voltage. the ?nal choice of r1 is made when the rest of the circuit design is complete. when the duty cycle drops below approximately 4%, the frequency is reduced, which reduces energy consumption under light load conditions. auto-restart operation when a fault condition, such as an output short circuit or open loop, prevents ?ow of an external current into the control pin, the capacitor c1 discharges towards 4.7 v. at 4.7 v, auto- restart is activated, which turns the mosfet off and puts the control circuitry in a low current fault protection mode. in auto-restart, linkswitch periodically restarts the power supply so that normal power supply operation can be restored when the fault is removed. figure 4. control characteristics. figure 5. power supply outline schematic. v out v in d2 c4 d s c c2 r1 r2 c1 d1 link s witc h pi-2715-112102 pi-2799-112102 internal current limit control current i c i dcs control current i c i cd1 control current i c duty cycle frequency i li m i dct 77% 30% 3.8% f osc f osc(low) auto-restart auto-restart auto-restart
4 i 2/05 lnk501 the characteristics described above provide an approximate cv/cc power supply output without the need for secondary side voltage or current feedback. the output voltage regulation is in?uenced by how well the voltage across c2 tracks the re?ected output voltage. this tracking is in?uenced by the value of the transformer leakage inductance which introduces an error. resistor r2 and capacitor c2 partially ?lter the leakage inductance voltage spike, reducing this error. this circuitry, used with standard transformer construction techniques, provides much better output load regulation than a linear transformer, making this an ideal power supply solution in many low power applications. if tighter load regulation is required, an optocoupler con?guration can be used while still employing the constant output current characteristics provided by linkswitch . optional secondary feedback figure 6 shows a typical power supply outline schematic using linkswitch with optocoupler feedback to improve output voltage regulation. on the primary side, the schematic differs from figure 5 by the addition of r3, c3 and optocoupler u1. resistor r3 forms a potential divider with r1 to limit the u1 collector emitter voltage. on the secondary side, the addition of voltage sense circuit components r4, vr1 and u1 led provide the voltage feedback signal. in the example shown, a simple zener (vr1) reference is used though a precision tl431 reference is typically needed to provide 5% output voltage tolerancing and cable drop compensation, if required. resistor r4 provides biasing for vr1. the regulated output voltage is equal to the sum of the vr1 zener voltage plus the forward voltage drop of the u1 led. resistor r5 is an optional low value resistor to limit u1 led peak current due to output ripple. manufacturer?s speci?cations for u1 current and vr1 slope resistance should be consulted to determine whether r5 is required. u1 is arranged with collector connected to primary ground and emitter to the anode of d1. this connection keeps the opto in an electrically quiet position in the circuit. if the opto was output v oltage t olerance en velope without optocoupler inherent cc to cv transition point load v ariation during batter y char ging v oltage feedbac k threshold characteristic with optocoupler t ypical inherent characteristic without optocoupler pi-2788-092101 output current figure 6. power supply outline schematic with optocoupler feedback. figure 7. in?uence of the optocoupler on the power supply output characteristic. lnk501 linkswitch 85-265 vac v out rtn s d c c1 c3 c2 u1 r4 r5 vr1 r1 r2 d1 r3 pi-2787-112102 u1
5 i 2/05 lnk501 figure 8. output characteristic with optocoupler regulation (reduced voltage feedback threshold). instead placed on the cathode side of d1, it would become a switching node, generating additional common mode emi currents through its internal parasitic capacitance. the feedback con?guration in figure 6 is simply a resistive divider made up of r1 and r3 with d1, r2, c1 and c2 rectifying, ?ltering and smoothing the primary winding voltage signal. the optocoupler therefore effectively adjusts the resistor divider ratio to control the dc voltage across r1 and therefore, the feedback current received by the linkswitch control pin. when the power supply operates in the constant current (cc) region, for example when charging a battery, the output voltage is below the voltage feedback threshold de?ned by u1 and vr1 and the optocoupler is fully off. in this region, the circuit behaves exactly as previously described with reference to figure 5 where the re?ected voltage increases with increasing output voltage and the linkswitch internal current limit is adjusted to provide an approximate cc output characteristic. note that for similar output characteristics in the cc region, the value of r1 in figure 5 will be equal to the value of r1+r3 in figure 6. when the output reaches the voltage feedback threshold set by u1 and vr1, the optocoupler turns on. any further increase in the power supply output voltage results in the u1 transistor current increasing, which increases the percentage of the re?ected voltage appearing across r1. the resulting increase in the linkswitch control current reduces the duty cycle according to figure 4 and therefore, maintains the output voltage regulation. normally, r1 and r3 are chosen to be equal in value. however, increasing r3 (while reducing r1 to keep r1 + r3 constant) increases loop gain in the cv region, improving load regulation. the extent to which r3 can be increased is limited by opto transistor voltage and dissipation ratings and should be fully tested before ?nalizing a design. the values of c2 and c3 are less important other than to make sure they are large enough to have very little in?uence on the impedance of the voltage division circuit set up by r1, r3 and u1 at the switching frequency. normally, the values of c2 and c3 in figure 6 are chosen equal to the value of c2 in figure 5, though the voltage rating may be reduced depending on the relative values of r1 and r2 discussed above. see applications section for typical values of components. figure 7 shows the in?uence of optocoupler feedback on the output characteristic. the envelope de?ned by the dashed lines represent the worst case power supply dc output voltage and current tolerances (unit-to-unit and over the input voltage range) if an optocoupler is not used. a typical example of an inherent (without optocoupler) output characteristic is shown dotted. this is the characteristic that would result if u1, r4 and vr1 were removed. the optocoupler feedback results in the characteristic shown by the solid line. the load variation arrow in figure 7 represents the locus of the output characteristic normally seen during a battery charging cycle. the two characteristics are identical as the output voltage rises but then separate as shown when the voltage feedback threshold is reached. this is the characteristic seen if the voltage feedback threshold is above the output voltage at the inherent cc to cv transition point also indicated in figure 7. figure 8 shows a case where the voltage feedback threshold is set below the voltage at the inherent cc to cv transition point. in this case, as the output voltage rises, the secondary feedback circuit takes control before the inherent cc to cv transition occurs. in an actual battery charging application, this simply limits the output voltage to a lower value. output v oltage output current v o(max) t olerance en velope without optocoupler characteristic with optocoupler po wer suppl y peak output po wer curve t ypical inherent characteristic without optocoupler pi-2790-112102 inherent cc to cv transition point load v ariation during batter y char ging characteristic observed with load v ariation often applied during laboratory bench testing v oltage feedbac k threshold
6 i 2/05 lnk501 however, in laboratory bench tests, it is often more convenient to test the power supply output characteristic starting from a low output current and gradually increasing the load. in this case, the optocoupler feedback regulates the output voltage until the peak output power curve is reached as shown in figure 8. under these conditions, the output current will continue to rise until the peak power point is reached and the optocoupler turns off. once the optocoupler is off, the control pin feedback current is determined only by r1 and r3 and the output current therefore folds back to the inherent cc characteristic as shown. since this type of load transition does not normally occur in a battery charger, the output current never overshoots the inherent constant current value in the actual application. in some applications it may be necessary to avoid any output current overshoot, independent of the direction of load variation. to achieve this goal, the minimum voltage feedback threshold should be set at v o(max) . this will ensure that the voltage at the cc to cv transition point of the inherent characteristic will always occur below the voltage feedback threshold. however, the output voltage tolerance is then increased, since the inherent cv characteristic tolerance below v o(max) is added to the tolerance of the optocoupler feedback circuit. applications example the circuit shown in figure 9 shows a typical implementation of an approximate constant voltage / constant current (cv/cc) charger using linkswitch . this design delivers 2.75 w with a nominal peak power point voltage of 5.5 v and a current of 500 ma. ef?ciency is greater than 70% over an input range of 85 vac to 265 vac. the bridge recti?er, br1, recti?es the ac input. resistor rf1 is a fusible type providing protection from primary side short circuits. the recti?ed ac is smoothed by c1 and c2 with inductor l1 forming a pi-?lter in conjunction with c1 and c2 to ?lter conducted emi. the switching frequency of 42 khz allows such a simple emi ?lter to be used without the need for a y capacitor while still meeting international emi standards. when power is applied, high voltage dc appears at the drain pin of linkswitch (u1). the control pin capacitor c3 is then charged through a switched high voltage current source connected internally between the drain and control pins. when the control pin reaches approximately 5.6 v relative to the source pin, the internal current source is turned off. the internal control circuitry is activated and the high voltage mosfet starts to switch, using the energy in c3 to power the ic. when the mosfet is on, the high voltage dc bus is connected to one end of the transformer primary, the other end being connected to primary return. as the current ramps in the primary of ?yback transformer t1, energy is stored. this energy is delivered to the output when the mosfet turns off each switching cycle. the secondary of the transformer is recti?ed and ?ltered by d6 and c5 to provide the dc output to the load. linkswitch dramatically simpli?es the secondary side by controlling both the constant voltage and constant current regions entirely from the primary side. this is achieved by monitoring the primary-side v or (voltage output re?ected). diode d5 and capacitor c4 form the primary clamp network. this both limits the peak drain voltage due to leakage inductance and provides a voltage across c4, which is equal to the v or plus an error due to the parasitic leakage inductance. resistor r2 ?lters the leakage inductance spike and reduces the error in the value of the v or . resistor r1 converts this voltage into a current that is fed into the control pin to regulate the output. during cv operation the output is regulated through control of the duty cycle. as the current into the control pin exceeds approximately 2 ma, the duty cycle begins to reduce, reaching 30% at a control pin current of 2.3 ma. under light or no-load conditions, when the duty cycle reaches approximately 4%, the switching frequency is reduced to lower energy consumption. if the output load is increased beyond the peak power point (de?ned by 0.5l p i lim 2 f), the output voltage and v or falls. the reduced control pin current will lower the internal linkswitch current limit (current limit control) providing an approximately constant current output characteristic. if the load is increased and the control pin current falls below approximately 1 ma, the control pin capacitor c3 will discharge and the supply enters auto-restart. current limit control removes the need for any secondary side current sensing components (sense resistor, transistor, opto coupler and associated components). removing the secondary sense circuit dramatically improves ef?ciency, giving the associated bene?t of reduced enclosure size. key application considerations design output power table 1 (front page) shows the maximum continuous output power that can be obtained under the following conditions: 1. the minimum dc input bus voltage is 90 v or higher. this corresponds to a ?lter capacitor of 3 f/w for universal input and 1 f/w for 230 vac or 115 vac input with doubler input stage. 2. design is a discontinuous mode ?yback converter, with nominal primary inductance value and a v or in the range 40 v to 60 v. continuous mode designs can result in loop instability and are therefore not recommended.
7 i 2/05 lnk501 figure 9. 2.75 w constant voltage/constant current (cv/cc) charger using linkswitch. figure 10. measured output characteristic of the circuit in figure 9. 100 0 200 300 400 500 600 700 output current (ma) output voltage (v) 0 1 2 3 4 5 6 7 8 9 10 pi-2964-112702 v in = 85 vac v in = 115 vac v in = 185 vac v in = 265 vac c1 4.7 f 400 v c2 4.7 f 400 v rf1 10 ? 1 w fusible l1 1 mh r1 20.5 k ? 1% r2 100 ? d5 1n4937 c4 0.1 f 100 v 116 t #34 aw g ee13 l p = 2.55 mh 15 t #30 aw g tiw 3 4 1 5 t1 6 d6 11dq06 c5 470 f 10 v 85-265 va c u1 lnk501 linkswitch 5.5 v, 500 ma rtn br1 1 a, 600 v pi-2904-080304 performance summary output power: 2.75 w efficiency: 72% no load consumption: 260 mw, 230 vac 200 mw, 115 vac c3 0.22 f 50 v d s c
8 i 2/05 lnk501 3. a secondary output of 5 v with a schottky recti?er diode. 4. assumed ef?ciency of 70%. 5. the part is board mounted with source pins soldered to suf?cient area of copper to keep the die temperature at or below 100 c. 6. an output cable with a total resistance of 0.2 ? . in addition to the thermal environment (sealed enclosure, ventilated, open frame, etc), the maximum power capability of linkswitch in a given application depends on transformer core size, ef?ciency, primary inductance tolerance, minimum speci?ed input voltage, input storage capacitance, output voltage, output diode forward drop, etc., and can be different from the values shown in table 1. in designs not required to meet 300 mw no-load consumption, the transformer can be designed with higher v or to extend power capability as noted in the following section. transformer design to provide an approximately cv/cc output, the transformer should be designed to be discontinuous; all the energy stored in the transformer is transferred to the secondary during the mosfet off time. energy transfer in discontinuous mode is independent of line voltage. the peak power point prior to entering constant current operation is de?ned by the maximum power transferred by the transformer. the power transferred is given by the expression p = 0.5l p i 2 f, where l p is the primary inductance, i 2 is the primary peak current squared and f is the switching frequency. to simplify analysis, the data sheet parameter table speci?es an i 2 f coef?cient. this is the product of current limit squared and switching frequency normalized to the feedback parameter i dct . this provides a single term that speci?es the variation of the peak power point in the power supply due to linkswitch . as primary inductance tolerance is part of the expression that determines the peak output power point (start of the cc characteristic) this parameter should be well controlled. for an estimated overall constant current tolerance of 20% the primary inductance tolerance should be 10% or better. this is achievable using standard low cost, center leg gapping techniques where the gap size is typically 0.08 mm or larger. smaller gap sizes are possible but require non-standard, tighter ferrite a l tolerances. other gapping techniques such as ?lm gapping allow tighter tolerances (7% or better) with associated improvements in the tolerance of the peak power point. please consult your transformer vendor for guidance. core gaps should be uniform. uneven core gapping, especially with small gap sizes, may cause variation in the primary inductance with ?ux density (partial saturation) and make the constant current region non-linear. to verify uniform gapping it is recommended that the primary current wave-shape be examined while feeding the supply from a dc source. the gradient is de?ned as di/dt = v/l and should remain constant throughout the mosfet on time. any change in gradient of the current ramp is an indication of uneven gapping. measurements made using a lcr bridge should not be solely relied upon; typically these instruments only measure at currents of a few milliamps. this is insuf?cient to generate high enough ?ux densities in the core to show uneven gapping. for a typical ee13 core using center leg gapping, a 0.08 mm gap (a lg of 190 nh/t 2 ) allows a primary inductance tolerance of 10% to be maintained in standard high volume production. this allows the ee13 to be used in designs up to 2.75 w with less than 300 mw no-load consumption. if ?lm gapping is used then this increases to 3 w. moving to a larger core, ee16 for example, allows a 3 w output with center leg gapping. the transformer turns ratio should be selected to give a v or (output voltage re?ected through secondary to primary turns ratio) of 40 v to 60 v. in designs not required to meet 300 mw no-load consumption targets, the transformer can be designed with higher v or as long as discontinuous mode operation is maintained. this increases the output power capability. for example, a 230 vac input design using an ee19 transformer core with v or >70 v, is capable of delivering up to 5 w typical output power. note: the linearity of the cc region of the power supply output characteristic is in?uenced by v or . if this is an important aspect of the application, the output characteristic should be checked before ?nalizing the design. output characteristic variation both the device tolerance and external circuit govern the overall tolerance of the linkswitch output characteristic. estimated peak power point tolerances for a 2.75 w design are 10% for voltage and 20% for current limit for overall variation in high volume manufacturing. this includes device and transformer tolerances and line variation. lower power designs may have poorer constant current linearity. as the output load reduces from the peak power point, the output voltage will tend to rise due to tracking errors compared to the load terminals. sources of these errors include the output cable drop, output diode forward voltage and leakage inductance, which is the dominant cause. as the load reduces, the primary operating peak current reduces, together with the leakage inductance energy, which reduces the peak charging of the clamp capacitor. with a primary leakage inductance of 50 h, the output voltage typically rises 30% over a 100% to 5% load change.
9 i 2/05 lnk501 at very light or no-load, typically less than 2 ma of output current, the output voltage rises due to leakage inductance peak charging of the secondary. this voltage rise can be reduced with a small preload with little change to no-load power consumption. the output voltage load variation can be improved across the whole load range by adding an optocoupler and secondary reference (figure 6). the secondary reference is designed to only provide feedback above the normal peak power point voltage to maintain the correct constant current characteristic. component selection the schematic shown in figure 5 outlines the key components needed for a linkswitch supply. clamp diode C d1 diode d1 should be either a fast (t r r <250 ns) or ultra-fast type (t rr <50 ns), with a voltage rating of 600 v or higher. fast recovery types are preferred, being typically lower cost. slow diodes are not recommended; they can allow excessive drain ringing and the linkswitch to be reverse biased. clamp capacitor C c2 capacitor c2 should be a 0.1 f, 100 v capacitor. low cost metallized plastic ?lm types are recommended. the tolerance of this part has a very minor effect on the output characteristic so any of the standard 5%, 10% or 20% tolerances are acceptable. ceramic capacitors are not recommended. the common dielectrics used such as y5u or z5u are not stable with voltage or temperature and may cause output instability. ceramic capacitors with high stability dielectrics may be used but are expensive compared to metallized ?lm types. control pin capacitor C c1 capacitor c1 is used during start-up to power linkswitch and sets the auto-restart frequency. for designs that have a battery load this component should have a value of 0.22 f and for resistive loads a value of 1 f. this ensures there is suf?cient time during start-up for the output voltage to reach regulation. any capacitor type is acceptable with a voltage rating of 10 v or above. feedback resistor C r1 the value of r1 is selected to give a feedback current into the control pin of approximately 2.3 ma at the peak output power point of the supply. the actual value depends on the v or selected during design. any 1%, 0.25 w resistor is suitable. output diode C d2 either pn fast, pn ultra-fast or schottky diodes can be used depending on the ef?ciency target for the supply, schottky diodes giving higher ef?ciency then pn diodes. the diode voltage rating should be suf?cient to withstand the output voltage plus the input voltage transformed through the turns ratio (a typical v or of 50 v requires a diode piv of 50 v). slow recovery diodes are not recommended (1n400x types). output capacitor C c4 capacitor c4 should be selected such that its voltage and ripple current speci?cations are not exceeded. linkswitch layout considerations primary side connections since the source pins in a linkswitch supply are switching nodes, the copper area connected to source together with c1, c2 and r1 (figure 5) should be minimized, within the thermal contraints of the design, to reduce emi coupling. the control pin capacitor c1 should be located as close as possible to the source and control pins. to minimize emi coupling from the switching nodes on the primary to both the secondary and ac input, the linkswitch should be positioned away from the secondary of the transformer and ac input. routing the primary return trace from the transformer primary around linkswitch and associated components further reduces coupling. y capacitor if a y capacitor is required, it should be connected close to the transformer secondary output return pin(s) and the primary bulk capacitor negative return. such placement will maximize the emi bene?t of the y capacitor and avoid problems in common- mode surge testing. quick design checklist as with any power supply design, all linkswitch designs should be veri?ed on the bench to make sure that component speci?cations are not exceeded under worst case conditions. note: in a linkswitch circuit, the source is a switching node. this should be taken into consideration during testing. oscilloscope measurements should be made with probe grounded to dc voltages such as primary return or dc rail but not to source. power supply input voltage should always be supplied using an isolation transformer. the following minimum set of tests is strongly recommended: 1. maximum drain voltage C verify that v ds does not exceed 675 v at highest input voltage and peak output power. 2. maximum drain current C at maximum ambient temperature, maximum input voltage and peak output power, verify drain current waveforms at start-up for any signs of transformer saturation and excessive leading edge current spikes. linkswitch has a minimum leading edge blanking time of
10 i 2/05 lnk501 figure 11. recommended circuit board layout for linkswitch using p package. + - hv dc input pi-2900-070202 transformer + - dc out d s s s s s c linkswitch y1- capacitor input filter capacitor output capacitor 2 00 ns to prevent premature termination of the on-cycle. verify that the leading edge current spike event is below current limit at the end of the 200 ns blanking period. 3. thermal check C at peak output power, minimum input voltage and maximum ambient temperature, verify that the temperature speci?cations are not exceeded for linkswitch , transformer, output diode and output capacitors. enough thermal margin should be allowed for part-to-part variation of the r ds(on) of linkswitch as speci?ed in the data sheet. under low line, peak power, a maximum linkswitch source pin temperature of 100 c is recommended to allow for these variations. 4. centered output characteristic C using a transformer with nominal primary inductance and at an input voltage midway between low and high line, verify that the peak power point occurs at the desired nominal output current, with the correct output voltage. if this does not occur then the design should be re?ned to ensure the overall tolerance limits are met. design tools up to date information on design tools can be found at the power integrations website: www.powerint.com.
11 i 2/05 lnk501 absolute maximum ratings (1,4) drain voltage .................................. ................ -0.3 v to 700 v drain peak current......................................400 ma control voltage ................................................ -0.3 v to 9 v control current (not to exceed 9 v)............100 ma storage temperature .......................................... -65 c to 150 c operating junction temperature (2) ..................... -40 c to 150 c lead temperature (3) ........................................................260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. 4. maximum ratings speci?ed may be applied, one at a time, without causing permanent damage to the product. exposure to absolute maximum rating conditions for extended periods of time may affect product reliability. thermal impedance thermal impedance: p or g package: ( ja ) ........................... 70 c/w (2) ; 55 c/w (3) ( jc ) (1) ............................................... 11 c/w notes: 1. measured on pin 2 (source) close to plastic interface. 2. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 3. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 12 (unless otherwise speci?ed) min typ max units control functions switching frequency f osc i c = i dct , t j = 25 c 38 42 46 khz low switching frequency f osc(low) duty cycle = dc lf t j = 25 c 26 30 34 khz duty cycle at low switching frequency dc lf frequency switching from f osc to f osc(low) , t j = 25 c 2.4 3.8 5.2 % low frequency duty cycle range dc (range) frequency = f osc(low) , t j = 25 c 1.8 3.15 4.5 % maximum duty cycle dc max i c = 1.5 ma 74 77 80 % pwm gain dc reg i c = i dct , t j = 25 c -0.45 -0.35 -0.25 %/ a control pin current at 30% duty cycle i dct t j = 25 c see figure 4 2.24 2.30 2.36 ma control pin voltage v c(idct) i c = i dct 5.5 5.75 6 v dynamic impedance z c i c = i dct , t j = 25 c 60 90 120 ?
12 i 2/05 lnk501 parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 12 (unless otherwise speci?ed) min typ max units shutdown/auto-restart control pin charging current i c(ch) t j = 25 c v c = 0 v -4.5 -3.25 -2 ma v c = 5.15 v -2.3 -1.3 -0.3 control/supply/ discharge current i cd1 t j = 25 c output mosfet enabled 0.95 1.06 1.14 ma i cd2 t j = 25 c output mosfet disabled 0.7 0.9 1.1 auto-restart threshold voltage v c(ar) 5.6 v auto-restart hysteresis voltage v c(ar)hyst 0.9 v auto-restart duty cycle dc (ar) short circuit applied at power supply output 8 % auto-restart frequency f (ar) s2 open c1 = 0.22 f (see figure 12) 300 hz circuit protection self-protection current limit i lim t j = 25 c di/dt = 90 ma/ s see note c 241 254 267 ma i 2 f coef?cient i 2 f t j = 25 c di/dt = 90 ma/ s see notes c, d 2547 2710 2873 a 2 hz current limit at auto-restart i lim(ar) i c = i cd1 , t j = 25 c 158 ma power up reset threshold voltage v c(reset) 1.5 2.75 4.0 v leading edge blanking time t leb i c = i dct , t j = 25 c 200 300 ns current limit delay t il(d) t j = 25 c 100 ns thermal shutdown temperature i c = i dct 125 135 c thermal shutdown hysteresis 70 c
13 i 2/05 lnk501 parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 12 (unless otherwise speci?ed) min typ max units output on-state resistance r ds(on) i d = 25 ma t j = 25 c 28 32 ? t j = 100 c 42 48 off-state drain leakage current i dss v c = 6.2 v v d = 560 v, t a = 125 c 50 a breakdown voltage bv dss see note b v c = 6.2 v, t a = 25 c 700 v drain supply voltage see note e 36 50 v notes: a. for speci? cations with negative values, a negative temperature coef?cient corresponds to an increase in magnitude with increasing temperature, and a positive temperature coef?cient corresponds to a decrease in magnitude with increasing temperature. b. breakdown voltage may be checked against minimum bv dss speci?cation by ramping the drain pin voltage up to but not exceeding minimum bv dss . c. i c is increased gradually to obtain maximum current limit at di/dt of 90 ma/ s. increasing i c further would terminate the cycle through duty cycle control. d. this parameter is normalized to i dct to correlate to power supply output current (it is multiplied by i dct (nominal)/ i dct ). e. it is possible to start up and operate linkswitch at drain voltages well below 36 v. however, the control pin charging current is reduced, which affects start-up time, auto-restart frequency, and auto-restart duty cycle. refer to the characteristic graph on control pin charge current (i c ) vs. drain voltage (figure 13) for low voltage operation characteristics.
14 i 2/05 lnk501 figure 12. linkswitch general test circuit. figure 13. i c vs. drain voltage. figure 14. duty cycle measurement. 120 100 80 40 60 20 0 0.0 2.0 4.0 8.0 6.0 10.0 12.0 14.0 control pin volta ge (v) pi-2895-102303 control pin current (ma) figure 15. control pin i-v characteristic. 90 50 60 70 80 0 2.15 2.25 2.35 2.45 2.55 2.65 control pin current (ma) duty cycle (%) pi-2902-051904 20 10 40 30 figure 16. duty cycle vs. control pin current. 2 1.2 1.6 0 0 2 0 4 0 6 0 8 0 100 drain voltage (v) control pin charging current (ma) pi-2901-071602 0.4 0.8 v c = 5.15 v d c s s s s s linkswitch pi-2894-031004 c1 0.22 f s2 40 v 40 v 750 ? 10 k ? s1
15 i 2/05 lnk501 typical performance characteristics figure 17. breakdown voltage vs. temperature. 1.200 1.000 0.800 0.400 0.600 0.200 0.000 -50 0 5 0 100 150 junction temperature ( c) pi-2896-062802 switching frequency (normalized for 25 c) 1.200 1.000 0.800 0.400 0.600 0.200 0.000 -50 -25 0 2 5 5 0 7 5 100 125 150 junction temperature ( c) pi-2897-062802 current limit (normalized for 25 c) 1.2 1 0.8 0.4 0.6 0.2 0 -50 0 5 0 100 150 temperature ( c) pi-2899-062802 pwm gain (normalized for 25 c) figure 18. switching frequency vs. temperature. figure 19. current limit vs. temperature. 1.1 1.0 0.9 -50 -25 0 2 5 5 0 7 5 100 125 150 junction temperature ( c) breakdown voltage (normalized to 25 c) pi-2213-012301 figure 22. pwm gain vs. temperature. 1.200 1.000 0.800 0.400 0.600 0.200 0.000 -50 0 5 0 100 150 junction temperature ( c) pi-2898-062802 i dct (normalized for 25 c) figure 21. i dct vs. temperature. figure 20. i 2 f coef?cient vs. temperature. 1.2 0.8 1.0 0.0 -50 -25 0 2 5 7 5 50 100 150 125 junction temperature ( c) i 2 f coefficient (normalized for 25 c) pi-2910-071602 0.2 0.6 0.4
16 i 2/05 lnk501 typical performance characteristics (cont.) figure 23. output characteristics (drain current vs. drain voltage). drain v oltage (v ) drain current (ma) 300 250 200 100 50 150 0 0 2 4 6 8 1 0 t case =25 c t case =100 c pi-2222-031401
17 i 2/05 lnk501 notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b 7/85) for standard dual-in-line (dip) package with .300 inch row spacing. 2. controlling dimensions are inches. millimeter sizes are shown in parentheses. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. the notch and/or dimple are aids in locating pin 1. pin 6 is omitted. 5. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. lead width measured at package body . 7. lead spacing measured with the leads constrained to be perpendicular to plane t. .008 (.20) .015 (.38) .300 (7.62) bsc (note 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) minimum .048 (1.22) .053 (1.35) .100 (2.54) bsc .014 (.36) .022 (.56) -e- pin 1 sea ting plane -d- -t - p08b dip-8b pi-2551-121504 d s .004 (.10) t e d s .010 (.25) m (note 6) .137 (3.48) minimum part ordering information linkswitch product family series number package identi?er g plastic surface mount dip p plastic dip lead finish blank standard (sn pb) n pure matte tin (pb-free) tape & reel and other options blank standard con?gurations tl tape & reel, 1 k pcs minimum, g package only lnk 501 g n - tl
18 i 2/05 lnk501 smd-8b pi-2546-121504 .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) .004 (.10) 0 - 8 .367 (9.32) .387 (9.83) .048 (1.22) .009 (.23) .053 (1.35) .032 (.81) .037 (.94) .125 (3.18) .145 (3.68) -d- notes: 1. controlling dimensions are inches. millimeter sizes are shown in parentheses. 2. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 3. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. pin 6 is omitted. 4. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 5. lead width measured at package body . 6. d and e are referenced datums on the package body . .057 (1.45) .068 (1.73) (note 5) e s .100 (2.54) (bsc) .372 (9.45) .240 (6.10) .388 (9.86) .137 (3.48) minimum .260 (6.60) .010 (.25) -e- pin 1 d s .004 (.10) g08b .420 .046 .060 .060 .046 .080 pin 1 .086 .186 .286 solder pad dimensions
19 i 2/05 lnk501 revision notes date d 1) released final data sheet. 7/02 e 1) enhanced tolerance with optocoupler designs. 2) updated p and g packages thermal impedance. 8/02 f 1) corrected minor errors in text and ?gures. 2) updated figure 6 and text description. 9/02 g 1) updated dip-8b and smd-8b package descriptions. 2) updated table 1 with no-load conditions. 3) corrected minor errors in text and ?gures. 4/03 h 1) added lead-free ordering information. 12/04 i 1) minor error and formatting corrections. 2/05
20 i 2/05 lnk501 for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability . power integrations does not assume any liability arising from the use of any device or circuit described herein. power integra tions makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations? patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signi?cant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch , tinyswitch , linkswitch , dpa-switch , ecosmart , pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?copyright 2005, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 807-808a, pacheer commercial centre, 555 nanjing rd. west shanghai, p.r.c. 200041 phone: +86-21-6215-5548 fax: +86-21-6215-2468 e-mail : chinasales@powerint.com china (shenzhen) rm 2206-2207, block a, electronics science & technology bldg. 2070 shennan zhong rd. shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india 261/a, ground floor 7th main, 17th cross, sadashivanagar bangalore, india 560080 phone: +91-80-5113-8020 fax: +91-80-5113-8023 e-mail: indiasales@powerint.com italy via vittorio veneto 12 20091 bresso mi italy phone: +39-028-928-6000 fax: + 39-028-928-6009 e-mail: eurosales@powerint.com japan keihin tatemono 1st bldg 2-12-20 shin-yokohama, kohoku-ku, yokohama-shi, kanagawa ken, japan 222-0033 phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road, #15-08/10 goldhill plaza, singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. james?s house east street, farnham surrey, gu9 7tj united kingdom phone: +44 (0) 1252-730-140 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760

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